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copyright ? cirrus logic, inc. 2011 (all rights reserved) http://www.cirrus.com cs5462 low-cost power/energy ic with pulse output features ? single-chip power measurement solution ? energy data linearity: 0.1% of reading over 1000:1 dynamic range ? on-chip functions: measures energy and performs energy-to-pulse conversions ? meets accuracy spec for iec 687/1036 ? on-chip system calibration option ? high-pass filter option for both i and v ? 2 available current input ranges ? on-chip 2.5 v reference (25 ppm/c typ) ? pulse outputs for stepper motor or mechanical counter ? on-chip energy direction indicator ? ground reference input signals with single supply ? high-frequency output for calibration ? on-chip power-on reset ? power supply configurations: va+ = +5 v; agnd = 0 v; vd+ = +3.3 v to 5 v description the cs5462 is a low-cost power meter solution combining two ??? analog-to-digital converters ?? adcs), an energy-to-frequency converter, and energy pulse outputs on a single chip. it is designed to accurately measure and calculate energy for single-phase 2- or 3- wire power metering applications with minimal external components. low-frequency energy outputs, e1 and e2 , supply average real power and can be used to drive a stepper motor or a mechanical counter; the high-frequency energy output fout can be used for calibration; and neg indicates negative power. the cs5462 has configuration pins which allow for direct configuration of pulse output format, pulse output frequency, current channel input range, high-pass filter option, and on-chip calibration. the cs5462 also has a power-on reset function which holds the part in reset until the supply reaches an operable level. ordering in formation: see page 16. i pga va+ iin+ iin- vin+ vin- vrefin vrefout high pass filter voltage reference x1 reset digital filter high pass filter x10 energy to pulse rate converter 4th order ?? modulator 2nd order ?? modulator digital filter x10,x50 dgnd / p1 energy direction calibration vd+ / p7 configuration inputs: on-chip calibration, pulse output mode / output frequency, hpf option, and current channel input range clock generator xout cpuclk e2 / p4 e1 / p5 fout / p6 igain cal1 freq cal0 neg/p2 p3 xin program select outputs for configuration agnd apr 11 ds547f1
cs5462 2 ds547f1 table of contents 1. general description ....................................................................................................... 3 2. pin description ........................................................................................................... ........ 3 3. characteristics/specifications ................................................................................. 5 analog characteristics ................................................................................................ 5 digital characteristics ................................................................................................. 7 switching characteristics .......................................................................................... 7 absolute maximum ratings ...... ................ ................ ................ ............. ............. ........... 8 3.1 theory of operation ....................................................................................................... .... 9 3.1.1 digital filters ......................................................................................................... 9 3.1.2 gain calibration .................................................................................................... 9 3.1.3 energy-to-frequency conversion ......................................................................... 9 4. functional description ............................................................................................... 10 4.1 programmable gain amplifier (pga) ............ ................................................................... 10 4.2 pulse-rate output ......................................................................................................... .. 10 4.2.1 stepper motor format. .. ...................................................................................... 10 4.2.2 mechanical counter format ................................................................................ 11 4.3 energy direction indicator ...................... .......................................................................... 11 4.4 internal calibration option ............................................................................................... 11 4.5 power-on reset ............................................................................................................ ... 11 4.6 oscillator characteristics ................................................................................................ .12 4.7 user defined settings ..................................................................................................... .12 4.8 basic application circuit configurations .......................................................................... 14 5. package dimensions ....................................................................................................... 1 5 6. ordering information .................................................................................................. 16 7. environmental, manufacturing, & hand ling information ............................ 16 8. revisions ................................................................................................................. ............ 16 list of figures figure 1. data flow ............................................................................................................ ............. 9 figure 2. pga settings......................................................................................................... ......... 10 figure 3. pulse output settings ................................................................................................ .... 10 figure 6. calibration options............................ ...................................................................... ....... 11 figure 7. power-on reset ....................................................................................................... ...... 12 figure 8. oscillator connection ................................................................................................ ..... 12 figure 9. calibration, frequency select, and pga select ............................................................ 12 figure 7. power-on reset ....................................................................................................... ...... 13 figure 8. typical connection diagram .......................................................................................... 1 4
cs5462 ds547f1 3 1. general description the cs5462 is a cmos monolithic power mea- surement device with an energy computation en- gine. the cs5462 combines a programmable gain amplifier, two ?? adc?s, system calibration, and energy-to-frequency conver sion circuitry on a sin- gle chip. the cs5462 is designed for energy measurement applications and is optimized to interface to a shunt or current transformer for current measurement, and to a resistive divider or transformer for voltage measurement. the current channel has a pro- grammable gain amplifier (pga) which provides two full-scale input level options. with a single +5 v supply on va+/agnd, both of the cs5462?s input channels accommodate common mode + signal levels between (agnd - 0.25 v) and va+. the cs5462 has three pulse output pins: e1 , e2 and fout . e1 and e2 can be used to directly drive a mechanical counter or stepper motor, or inter- face to a microcontroller. the fout pin conveys average real power at a pulse frequency many times higher than that of the e1 or e2 pulse fre- quency, allowing for high speed calibration. 2. pin description clock generator crystal out crystal in 1,24 xout, xin - a single stage amplifier inside the chip is connected to these pins and can be used with a crystal to provide the syst em clock for the device. alternat ively, an external clock can be supplied to the xin pin to provi de the system clock for the device. cpu clock output 2 cpuclk - output of on-chip oscillator which can drive one standard cmos load. control pins calibration pins 5, 23 cal0, cal1 - must be tied to a program select pin for calibration. program selects 1,2,3,4,5,6 4,6,20,22,21, 18,3 p1, p2, p3, p4, p5, p6, p7 - used in calibration, frequency select, and input gain select. frequency select 7 freq - must be tied to a program select pin to determine the frequency of e1 and e2 . current channel gain select 17 igain - must be tied to a program select pin to determine the full-scale input voltage range of the current channel. reset 19 reset - low activates reset energy pulse outputs energy output 1 4 , 2 3 21, 22 e1 , e2 - the energy output pin issues a fixed-width pul se train output with a rate proportional to real energy. high freq output 5 18 fout - outputs energy pulses at a maximum rate of 10 khz. used for calibration purposes. negative energy indicator 6 6 neg - low indicates negative energy. vrefin 12 voltage reference input vrefout 11 voltage reference output vin- 10 differential voltage input vin+ 9 differential voltage input dgnd 8 digital ground freq 7 frequency select neg / p2 6 neg energy indicator / prog sel 2 cal0 5 calibration pin 0 dgnd / p1 4 digital ground / prog sel 1 vd+ / p7 3 positive power supply / prog sel 7 cpuclk 2 cpu clock output xout 1 crystal out agnd 13 analog ground va+ 14 positive analog supply iin- 15 differential current input iin+ 16 differential current input igain 17 gain select fout / p6 18 high frequency output / prog sel 6 reset 19 reset p3 20 program select 3 e1 / p5 21 energy output 1 / prog sel 5 e2 / p4 22 energy output 2 / prog sel 4 cal1 23 calibration pin 1 xin 24 crystal in
cs5462 4 ds547f1 notes: 1 pin number 4 is described as digital ground (dgnd) and also p1 2 pin number 3 is described as posi tive power supply (vd+) and also p7 3 pin number 22 is described as energy output 2 (e2 ) and also p4 4 pin number 21 is described as energy output 1 (e1 ) and also p5 5 pin number 18 is described as high frequency output (fout ) and also p6 6 pin number 6 is described as negative energy indicator (neg ) and also p2 analog inputs/outputs differential voltage inputs 9,10 vin+, vin- - differential analog input pins for voltage channel. voltage reference output 11 vrefout - the on-chip voltage reference is output from this pin. the voltage reference has a nominal magnitude of 2.5 v and is referenced to the agnd pin on the converter. voltage reference input 12 vrefin - the voltage input to this pin establishes th e voltage reference for the on-chip modula- tor. differential current inputs 16,15 iin+, iin- - differential analog input pins for current channel. power supply connections positive digital supply 3 vd+ - the positive digital supply. digital ground 4* dgnd - digital ground analog ground 13 agnd - analog ground positive analog supply 14 va+ - the positive analog supply.
cs5462 ds547f1 5 3. characteristics/specifications ? min / max characteristics and specifications are guaranteed over all operating conditions. ? typical characteristics and specifications are mea- sured at nominal supply voltages and t a = 25 c. ? agnd = dgnd = 0 v. all voltages with respect to 0v. ? cal0 and cal1 are connected to p4 unless other- wise noted. analog characteristics notes: 1. applies afte r system calibration 2. va+ = vd+ = 5 v 10 %; mclk = 4.096 mhz parameter symbol min typ max unit analog inputs (current channel) maximum differential input voltage range (gain = 10) {(i in +)-(i in -)} (gain = 50) i in - - - - 500 100 mv p-p mv p-p input capacitance (all gain ranges) c in i -25-pf effective input impedance (all gain ranges)(note 2) z in i 30 - - k ? analog inputs (voltage channel) maximum differential input voltage range {(v in +)-(v in -)} v in --500mv p-p input capacitance c in v -0.2-pf effective input impedance (note 2) z in v 5- -m ? accuracy (energy outputs) offset error vos - .01 - %f.s. full-scale error (note 1) fse - .1 - %f.s.
cs5462 6 ds547f1 analog characteristics (continued) notes: 3. all outputs unloaded . all inputs cmos level. 4. definition for psrr: vrefin tied to vrefout, va+ = vd+ = 5 v, a 150 mv zero-to-peak sine wave (frequency = 60 hz) is imposed onto the +5 v supply voltage at va+ and vd+ pins. the ?+? and ?-? input pins of both input channels are shorted to va-. then the cs5462 is put into an internal test mode and di gital output data is collected for the channel under test. the zero-peak value of the digita l sinusoidal output signal is determined, and this value is converted into the zero-peak value of the sinusoidal voltage that would need to be applied at the channel?s inputs, in order to cause the same digital sinusoidal output. this voltage is then defined as veq. psrr is then (in db): vrefout reference output voltage notes: 5. the voltage at vrefout is measured across th e temperature range. from these measurements the following formula is used to calculate the vrefout temperature coefficient:. parameter symbol min typ max unit dynamic characteristics high pass filter pole frequency -3 db - 0.5 - hz power supplies power supply currents i a+ i d+ (vd+ = 5 v) i d+ (vd+ = 3.3 v) psca pscd pscd - - - 1.3 2.9 1.7 - - - ma ma ma power consumption (vd+ = 5 v) (note 3) (vd+ = 3.3 v) pc - - 21 11.6 25 - mw mw power supply rejection ratio (50, 60 hz) (note 4) voltage channel (gain = 10) current channel (gain = 10) (gain = 50) psrr psrr psrr 48 75 56 - - - - - - - - db db db parameter symbol min typ max unit reference output output voltage refout +2.4 +2.6 v vrefout temperature coefficient tc vref 25 60 ppm/c load regulation (output current 1 ? a source or sink) ? v r 610 mv reference input input voltage range vrefin +2.4 +2.5 +2.6 v input capacitance - 4 - pf input cvf current - 25 - na psrr 20 0.150v v eq ----------------- - ?? ?? ?? log ? = (vrefout max - vrefout min ) vrefout avg ( ( 1 t a max - t a min ( ( 1.0 x 10 ( ( 6 tc vref =
cs5462 ds547f1 7 digital characteristics (note 6) notes: 6. all measurements performed under static conditions. switching characteristics 7. if external mclk is used, then the duty cycle mu st be between 45% and 55% to maintain this specification. 8. specified using 10% and 90% points on wave-form of interest. output loaded with 50 pf. 9. oscillator start-up time varies with crystal parameters. this specificat ion does not apply when using an external clock source. parameter symbol min typ max unit high-level input voltage xin reset v ih (vd+) - 0.5 0.8 ? vd+ - - - - v v low-level input voltage (vd = 5 v) xin reset v il - - - - 1.5 0.2 ? vd+ v v low-level input voltage (vd = 3.3 v) xin reset v il - - - - 0.3 0.2 ? vd+ v v high-level output voltage (except xout) i out = +5 ma v oh (vd+) - 1.0 - - v low-level output voltage (except xout) i out = -5 ma v ol --0.4v input leakage current i in -110a digital output pin capacitance c out -5-pf drive current fout , e1 , e2 , neg , cpuclk 90 ma parameter symbol min typ max unit master clock frequenc y internal gate osc illator mclk 3 4.096 5 mhz master clock duty cycle 40 - 60 % cpuclk duty cycle (note 7) 40 60 % rise times any digital input (note 8) any digital output t rise - - - 50 1.0 - s ns fall times any digital input (note 8) any digital output t fall - - - 50 1.0 - s ns start-up oscillator start-up time xt al = 4.096 mhz (note 9) t ost -60-ms
cs5462 8 ds547f1 absolute maximum ratings warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not gu aranteed at these extremes. 10. va+ and agnd must sa tisfy {(va+) - (agnd)} ? + 6.0 v. 11. vd+ and agnd must satisfy {(vd+) - (agnd)} ? + 6.0 v. 12. va+ and vd+ can differ by as much as 200 mv, as long as va+ > vd+. 13. applies to all pins including continuous over-v oltage conditions at the analog input pins. 14. transient current of up to 10 0 ma will not cause scr latch-up. 15. maximum dc input current for a power supply pin is 50 ma. 16. total power dissipation, including all input currents and output currents. parameter symbol min typ max unit dc power supplies (notes 10, 10 and 12) positive digital positive analog vd+ va+ -0.3 -0.3 - - +6.0 +6.0 v v input current, any pin except supplies (notes 13, 14, 15) i in --10ma power dissipation (note 16) p d --500mw analog input voltage all analog pins v ina - 0.3 - (va+) + 0.3 v digital input voltage all digital pins v ind -0.3 - (vd+) + 0.3 v ambient operating temperature t a -40 - 85 c storage temperature t stg -65 - 150 c
cs5462 ds547f1 9 3.1 theory of operation a computational flow diagram for the two data paths is shown in figure 1. the analog waveforms at the voltage/current channel inputs are subject to the gains of the input pgas. 3.1.1 digital filters the modulators convert the analog input voltages on the i and v channels to a digital bitstream; which is then filtered by the digital filter section. the digi- tal filter is composed of low pass sinc 3 and iir fil- ters. the iir filters are used to compensate for the magnitude roll-off of the low pass filter section. both channels provide a high-pass filter option which can be engaged into the signal path to re- move the dc content from the current/voltage signal before the energy calculations are made. 3.1.2 gain calibration after being filtered, the instantaneous voltage and current digital codes are used to calculate real av- erage power. this power is then adjusted based on the internal calibration setting defined at startup. calibrating the cs5462 is done by externally con- necting the configuration input pins, cal1 and cal0, to the program select output pins, p1 - p7, in a particular sequence. these connections will in- ternally compensate for small gain errors. 3.1.3 energy-to-frequency conversion the calibrated energy value is then converted into a pulse output stream with a average frequency proportional to the measured energy. pulse output pins e1 and e2 can be set to lower frequencies to directly drive a stepper motor or a mechanical counter or interface a microcontroller or infrared led. the fout pulse output pin is set to max fre- quency of 10 khz. with full scale inputs on both the current and voltage channels fout will output pulses with an average frequency of 10 khz. x vin iin pga gain select hpf select freq select energy to pulse rate converter e1 e2 fout calibration digital filters digital filters 4 th order ?? modulator 2 nd order ?? modulator pga 10x x on-chip configuration output mode select hpf hpf figure 1. data flow
cs5462 10 ds547f1 4. functional description 4.1 programmable gain amplifier (pga) the cs5462 is equipped with a pga on the current channel. while the voltage channel is always set to a 10x differential input voltage range (500 mv p-p ), the current channel can be set to one of two differ- ent input ranges. the maximum differential voltage range on the current channel can be set to 10x (500 mv p-p ) and 50x (100 mv p-p ). the gain setting of the current channel?s pga and also the high pass filter option are selected by con- necting the igain pin to one of seven program se- lect output pins. for all applications the igain pin must be tied to one and only one program select pins. figure 2 below shows the different options that can be selected at startup. these seven differ- ent options allow the cs5462?s pga to be set up in either 10x or 50x mode and enable or disable the high pass filters in either of the voltage or the cur- rent channels. during startup the cs5462 will scan the igain in- put pin and determine which program select out- put it is connected to and then set the pga and hpf?s accordingly. 4.2 pulse-rate output e1 and e2 pins provide a simple interface from which signed energy can be accumulated. e1 and e2 can be set to either stepper motor mode or me- chanical counter mode. the connectivity of the freq pin determines the pulse output mode and also the maximum frequency for e1 and e2 . figure 3 below describes the options for e1 and e2 . for all applications freq must be connected to one and only one of the program selects outputs (p1 - p7). the frequency setting chosen using the above table is equal to the set pulse rate frequency if and only if a full-scale signal is applied to each channel. as the input signal decreases the pulse rate and pulse width will decrease by a percentage equal to the product of the percentages of full- scale inputs across each channel. for example, if if freq is connected to p5, the maximum pulse output rate is 4 hz. assuming 500 mv is selected as full scale on each channel, 400 mv is measured on current and voltage channels. 400 mv is 80% of full scale. since power is the product of current and voltage the pulse outputs will be 80% * 80% = 64% of full scale. since 4 hz is the set full scale output rate, pulses should appear on e1 and e2 at a 64% * 4 hz = 2.56 hz rate. 4.2.1 stepper motor format. in stepper motor mode the cs5462 produces alter- nating pulses on e1 and e2 . this pulse format is designed to directly drive a stepper motor. each pin produces active-low pulses with frequency de- pendent pulse widths. the figure below shows the frequency and corresponding pulse width for each option. igain 500mv p-p 10x p1 p2 p3 p4 p5 100mv p-p 50x 500mv p-p 10x 100mv p-p 50x p6 p7 500mv p-p 10x 100mv p-p 50x 500mv p-p 10x no hpf no hpf hpf both hpf both hpf ich hpf ich hpf vch figure 2. pga settings freq 0.25 hz / step p1 p2 p3 p4 p5 0.5 hz / step 1 hz / step 2 hz / step 4 hz / step p6 p7 2 hz / mech cnt 16 hz / mech cnt figure 3. pulse output settings 0.25 hz 0.5 hz 250 ms 250 ms pulse width frequency p1 p2 freq connected to: 1 hz 2 hz 250 ms 250 ms p3 p4 4 hz 125 ms p5 e1 pulse width e2
cs5462 ds547f1 11 4.2.2 mechanical counter format in mechanical counter mode, the cs5462 produc- es pulses on e1 and e2 which can be used to drive a bi-directional mechanical counter. each pin pro- duces active-low pulses which have pulse widths of 125 ms or 15 ms, depending on the frequency selected. in the figure below, the frequency and corresponding pulse width is shown for each op- tion available. in this mode when energy is posi- tive, the pulses appear on e1 ; when energy is negative, pulses appear on e2 . 4.3 energy direction indicator for either pulse output mode, the neg pin can be used to indicate the direction of the energy calcu- lated. the neg pin is updated at the sample rate of the converter. if negative energy is detected the neg pin will become active low and will remain ac- tive low until positive energy is detected. 4.4 internal calibration option for most power meter applications the standard accuracy requirements require the meter be cali- brated to within a certain percentage. calibrating a cs5462 meter can be done a number of ways. one calibration method is to externally adjust the front-end input circuit by using a potentiometer or resistor network. by adjusting the amount of gain in the resistor divider on the front end the energy out- puts can be adjusted to fit the accuracy required. although this method is available, it may be costly to add the additional components and the accuracy required is often difficult to achieve. as an alterna- tive the cs5462 is designed to allow the user to calibrate the part without the need for external po- tentiometers or resistor networks. the cs5462 provides a digital on-chip calibration solution. this digital alternative can calibrate energy registration error to within 0.1% without any analog adjust- ments. this calibration is accomplished by connecting each configuration input pin, cal1 and cal0, to one of the program select output pins, p1 - p7. at startup the cs5462 will scan the cal1 and cal0 pins to discern what connections are made, and then calibrate the gain accordingly. cal1 and cal0 each have seven options which allows for 49 different steps of 0.2% between +4.8% and -4.8% of expected energy output. be- fore startup, cal1 and cal0 must each be con- nected to only one of the program select pins. to calibrate the cs5462: 1. connect cal1 and cal0 to p4. this connection will adjust the energy outputs by 0%. 2. apply known current and voltage signals to the inputs of the cs5462. 3. measure the average pulse output frequency of fout , e1 , or e2 . 4. the average frequency wi ll be within some per- centage of the expected frequency. depending on the output of the uncalibra ted chip, the cal0 and cal1 pins can be adjust ed using the above options (see ?user defined set tings? on page 12 for more on calibration) . 4.5 power-on reset the cs5462 is equipped with internal circuitry that will put the chip into reset if power supply is lost. this is particularly useful in black-out or brown-out situations in which the pow er supply temporarily in- terrupted. the cs5462 will enter into reset if the power drops below 2.5 v. the chip will remain in reset until the supply rises to 4 v (see figure 6) at pulse width e1 pulse width positive energy negative energy e2 2 hz 16 hz 125 ms 15 ms pulse width frequency p6 p7 freq connected to: cal1 +4.2% p1 p2 p4 p6 p7 +2.8% 0% -2.8% -4.2% cal0 +0.6% +0.4% 0% -0.4% -0.6% p3 p5 +1.4% -1.4% +0.2% -0.2% figure 6. calibration options
cs5462 12 ds547f1 which time the cs5462 will configure itself and re- sume normal operation. 4.6 oscillator characteristics xin and xout are the input and output of an in- verting amplifier which can provide oscillation and can be configured as an on-chip oscillator, as shown in figure 8. the oscill ator circuit is designed to work with a quartz crystal or a ceramic resona- tor. to reduce circuit cost, two load capacitors c1 and c2 are integrated in the device, one between xin and dgnd, one between xout and dgnd. lead lengths should be minimized to reduce stray capacitance. to drive the device from an external clock source, xout should be left unconnected while xin is driven by the external circuitry. there is an amplifier between xin and the digital section which provides cmos level signals. this amplifier works with sinusoidal inputs so there are no prob- lems with slow edge times. 4.7 user defined settings example: design a hybrid stepper motor meter with an 2 hz maximum pulse output frequency on the e1 , e2 pins with 500 mv p-p signal on the in- puts of the current and voltage channels and the high pass filter enabled on the current channel on- ly. using the figure below these settings can be se- lected with two connections. by directly connecting freq with p4 and igain with p5 the cs5462 is configured to drive a step- per motor with a maximum pulse output rate of 2 hz, to support an input range of 500 mv p-p , and to remove all dc content on the current signals by enabling the hpfs on the ich. the cs5462 is now ready for calibration. before applying power to the chip, connect the cal0 and cal1 pins to p4. this will select 0% + 0% = 0% gain adjustment. after making this connection the cs5462 is ready to be calibrated. once power is applied the cs5462 will begin a startup sequence in which it will scan the freq, igain, cal0, and cal1 pins. after determining which connections are made the freq, igain, cal0, and cal1 pins will become high impedance inputs and the part will begin normal operation and start converting. if on-chip calibration is required place known voltages across the inputs on iin and vin. for example, 150 mv rms = ~424.26 mv p-p will be used for both the current and voltage inputs. 424.26 mv p-p is ~84.853% of the maximum full scale input of both the current and voltage chan- nels. with this input on both channels the expected pulse output frequency is 84.853% * 84.853% = 72% of full scale. this reset reset normal operation 5 v 4 v 2.5 v 1 v 0 v time supply voltage figure 7. power-on reset oscillator circuit dgnd xin xout c1 c1 = 22 pf c2 c2 = figure 8. oscillator connection p1 p2 p3 p4 p5 p6 p7 10x 50x 10x 50x 50x 10x 10x cal1 cal0 0.25 hz (stp) freq +4.2% +2.8% +1.4 0 -1.4% -2.8% -4.2% igain +0.6% +0.4% +0.2% 0 -0.2% -0.4% -0.6% 0.5 hz (stp) 1 hz (stp) 2 hz (stp) 4 hz (stp) 4 hz (mc) 16 hz (mc) 500mv 100mv 500mv 100mv 100mv 500mv 500mv no hpf no hpf hpf both hpf both hpf ich hpf vch hpf ich figure 9. calibration, frequency select, and pga select
cs5462 ds547f1 13 means that e1 and e2 should have an average pulse output frequency of 2 hz * 72% = 1.44 hz and fout should have an average pulse output frequency of 10 khz * 72% = 7.2 khz. assuming that fout is used for calibration (although the gain error will be the same for e1 and e2 ), fout should be measured to find the gain error. suppose the measured pulse output frequency is 6.966 khz in- stead of 7.2 khz. 6.996 khz is 96.76% of 7.2 khz. this means that the gain error is 96.76% - 100% = -3.24%. this error can be calibrated out by connecting cal1 to p2 and cal0 to p2 (see fig- ure 7 for all connection options). this will adjust the pulse rate frequency by 2.8% + 0.4% = 3.2% (since the smallest calibration step size is 0.2%, 3.2% is the closest value that can offset the error of -3.24). after these connections are made the av- erage pulse output frequency of fout , e1 , and e2 will have a gain error less than or equal to -0.04% of full scale. p3 +4.4% +3.0% +1.6% +0.2% -4.0% -2.6% -1.2% +4.8% p1 p2 p3 p4 p5 p6 p7 p1 p2 p4 p5 p6 p7 +4.6% +3.4% +3.2% +2.0% +1.8% +0.0% +0.6% +0.4% +4.2% +4.0% +3.8% +2.8% +2.6% +2.4% +1.4% +1.2% +1.0% +3.6% +2.2% +0.8% cal0 connected to: cal1 connected to: -4.8% -4.6% -4.4% -3.4% -3.2% -3.0% -2.0% -1.8% -1.6% -0.6% -0.4% -0.2% -4.2% -3.8% -2.8% -2.4% -1.4% -1.0% -3.6% -2.2% -0.8% figure 7. power-on reset
cs5462 14 ds547f1 4.8 basic application circuit configurations figure 9 shows the cs5462 configured to measure power in a single-phase 2-wire system while oper- ating in a single supply configuration. in this dia- gram, the shunt resistor used to monitor the line current is connected on the ?line? (hot) side of the power mains. in most residential power metering applications, the power meter?s current-sense shunt resistor is intentionally placed on the hot side of the power mains in order to detect a subscriber?s attempt to steal power. in this type of shunt-resistor configuration, the common-mode level of the cs5462 must be referenced to the hot side of the power line. this means that the common-mode po- tential of the cs5462 will typically oscillate to very high voltage levels, as well as very low voltage lev- els, with respect to earth ground potential. jumpers for calibration, freq select and gain select mechanical counter dgnd / p1 edir / p4 vd+ / p7 neg / p2 p3 cal0 cal1 freq igain eout fout / p6 xout xin cpuclk dgnd va- vrefout vrefin iin+ iin- vin- vin+ agnd 3 15 14 9 10 16 12 11 13 8 2 24 1 18 21 22 17 7 5 23 20 6 4 120 vac ???? ????? ????? ??? nv ? ??? ? f ??? ? f ??? ? f r shunt ??? ? f r 1 r 2 nl agnd va+ e2 / p4 e1 / p5 r i+ r i- r v- c idiff c vdiff c v- c v+ c i+ c i- stepper motor or figure 8. typical connection diagram
cs5462 ds547f1 15 5. package dimensions notes: 1. ?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion /intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximu m material condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the fl at section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.084 -- -- 2.13 a1 0.002 0.006 0.010 0.05 0.13 0.25 a2 0.064 0.068 0.074 1.62 1.73 1.88 b 0.009 -- 0.015 0.22 -- 0.38 2,3 d 0.311 0.323 0.335 7.90 8.20 8.50 1 e 0.291 0.307 0.323 7.40 7.80 8.20 e1 0.197 0.209 0.220 5.00 5.30 5.60 1 e 0.022 0.026 0.030 0.55 0.65 0.75 l 0.025 0.03 0.041 0.63 0.75 1.03 ? 0 4 8 0 4 8 jedec #: mo-150 controlling dimension is millimeters. 24l ssop package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view ?
cs5462 16 ds547f1 6. ordering information 7. environmental, manufactur ing, & handling information * msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. 8. revisions model temperature package CS5462-ISZ (lead free) -40 to +85 c 24-pin ssop model number peak reflow temp msl rating* max floor life CS5462-ISZ (lead free) 260 c 3 7 days revision date changes a1 mar 2003 initial release pp1 oct 2003 initial release for preliminary product information f1 apr 2011 removed lead-containing (pb) device ordering information. added msl data. contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warrant y of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual proper ty rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general di stribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential risks of death, pe rsonal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not desi gned, authorized or warranted for use in products surgically implante d into the body, automo tive safety or security devices, life support products or other crit- ical applications. inclusion of cirrus prod ucts in such applications is understood to be fully at the custo mer's risk and cir- rus disclaims and makes no warranty, express, statutory or im plied, including the implied wa rranties of merchantability and fitness for particular purpose, with regard to any cirrus produc t that is used in such a mann er. if the customer or custom- er's customer uses or permits the use of ci rrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including at- torneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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